1. Field of Invention
The present invention pertains to data processing systems, generally, and more particularly to data processing systems using a very fast access semiconductor memory array.
2. Description of the Related Art
In the prior art, data processing systems transfer an entire row of data bits from a dynamic random access memory into a serial register for readout. From the serial register, the entire row of data bits may be read out in a serial sequence. We know that this operation puts limits on the speed of some data processing systems.
In order to improve the speed of access of the first bit of a serial readout operation of a random access memory, the initial tap (column) address is latched into a register for accessing the selected first bit directly from the memory array rather than from the serial register. The selected initial bit is transmitted through a first data line from the array directly to a first input of a multiplexer. Subsequent bits are transmitted from taps associated with the sequential stages of the serial register. Addressing the stages of the serial register is accomplished by presetting a tap address counter to a count state equivalent to the initial tap address and incrementing that count state in response to the readout clock.
Address decoding is designed to enable simultaneous readout from pairs of adjacent serial register stages. The two bits of information (one from an odd column address and one from an even column address) are transmitted through separate leads, each associated with a different input to an odd/even multiplexer, or selector. The least significant bit of the tap address determines whether the bit from the odd column address or the bit from the even column address is transmitted through the multiplexer.
When the initial tap address is an even number, the first and second bits are accessed very rapidly. The first bit is accessed directly from the memory array, as previously described. The second bit is accessed from an addressed tap of the serial register. That tap is previously addressed because of the paired adjacent stages of the serial register addressing scheme, as previously described. As soon as the least significant bit of the tap address counter is incremented, the second bit is transmitted through the odd/even multiplexer.
A problem arises, however, when the initial tap address is an odd number. The first bit is accessed very rapidly directly from the memory array, again as previously described. Access of the second bit is much slower under these circumstances because when the tap address is incremented, the incremented count must ripple through at least first and second stages of the tap address counter, some interconnecting leads, and the decoder circuitry before the second tap address is valid. The delay caused by the ripple through increment addressing of the second tap is sufficiently long that the operating speed of some data processing systems must be reduced to wait for data being read out of the memory.